1. Field of the Invention
The invention relates to LSI physical designing method, program, and apparatus for making a layout design by a layout and wiring of circuit blocks and cells on the basis of a floor plan and, more particularly, to LSI physical designing method, program, and apparatus in which a non-rectangular area is handled as a physical design unit such as circuit block, cell, or the like.
2. Description of the Related Arts
In recent years, in an LSI designing system, a gate scale to a chip size has been increasing due to the realization of advanced functions. In a layout design known as an LSI physical design for converting a designed circuit diagram into a layout wiring of a device having a physical shape and dimensions, an efficient using method of a chip shape is demanded. In the conventional layout design, a layer layout design in which the circuit diagram is separated into layers such as chip, circuit block, and cell and designing operations are executed in parallel is generalized. In such a layer layout design, only a rectangular area is handled as a shape of a physical design unit of a lower layer such as circuit block or cell.
Refer to JP-A-5-181936, JP-A-6-124321, JP-A-5-160375, JP-A-5-243383, JP-A-9-147009, JP-A-10-189746, and JP-A-2003-303217.
However, in such a conventional layer layout design, since only a rectangular area is permitted as a physical design unit such as circuit block, cell, or the like, for example, in the case where the cells are arranged in the rectangular area of the circuit block, the cells are not always uniformly distribution-arranged in the rectangular area and there is such a problem that a dead space in which a cell layout or wiring is not locally performed is liable to occur.